Three Days National Seminar at Madanapalle Institute of Technology and Science

SERB SPONSORED 3-Day National Seminar on “Recent Trends and Challenges in VLSI Circuits, Devices and Architectures”

January 04, 2024

Organization: Madanapalle Institute of Technology and Science

Organization Profile: Madanapalle Institute of Technology and Science (MITS), originated under the auspices of Ratakonda Ranga Reddy Educational Academy under the proactive leadership of President and Dr. N. Vijaya Bhaskar Choudary, Ph.D., Secretary & Correspondent of the Academy. MITS is governed by a progressive management that never rests on laurels and has been striving conscientiously to develop it as one of the best centers of Academic Excellence in India. The Institution’s profile is firmly based on strategies and action plans that match changing demands of the nation and the student’s fraternity. MITS enjoys constant support and patronage of NRI’s with distinguished academic traditions and vast experience in Engineering & Technology.

Event: National Seminar

Title of the Seminar: Recent Trends and Challenges in VLSI Circuits, Devices and Architectures

About Seminar: The 3-Day national seminar is organized with the concept of Industry-Institute Coordination to improve the opportunities for students, research scholars, faculty. Seminar is planned with a vision to provide an exposure to recognize the importance of VLSI circuits, devices, and architectures for Semiconductor sector. This seminar will address the importance of low power VLSI circuits in modern era and key challenges of dynamic power and static power dissipations in circuits and discuss about key challenges and limitations of TUNNEL FET device. The participants can understand the basics of tunnel FET and operation of non-volatile memory devices such as RRAM devices. The speakers will demonstrate the role of VLSI architectures in signal processing and Encryption, and the testing concepts in system level for verification.

This Program is designed to provide a platform for the academicians with a view to explore the information on the progress of VLSI.

Who can attend: Faculty and Student (BTech, MTech)/PhD research scholars working in the area of VLSI.

Specific research attend be covered:

  • Digital VLSI Test and Verification
  • Low Power VLSI Circuits
  • Tunnel FET device and Basic Concepts of Non-Volatile Memory Devices
  • VLSI Architectures for Signal Processing
  • Suppressing Leakage Mechanisms in Emerging Device Architectures for sub 10 nm technology node devices
  • Optimization of Placement and Routing in ASIC design
  • VLSI Architectures for AES Encryption
  • FPGA Architectures for Machine Learning
  • Nano Spintronic Devices
  • VLSI Design and Intellignet Systems

Seminar Duration: 23rd January to 25th  January 2024 (Tuesday to Thursday).

Last date for the receipt of applications: 18th January 2023

Mode: Offline

Registration link:

For any Queries Please contact Dr. Nehru Kandasamy, MITS. Mobile: +919940529189

email: [email protected]

Reference:  Brochure Link:

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